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标题: 怎樣对一個数字verilog程序编写的流水線加法器做PT和ASTRO [打印本页]

作者: 鬼丸 时间: 2020-3-2 09:19
标题: 怎樣对一個数字verilog程序编写的流水線加法器做PT和ASTRO
文章简介：我在做一个verilog编写的8位四级流水线加法器，这是我第一次做全流程{stage1_cout,stage1_sum}<={{1'b0,sta{stage2_cout,stage2_sum}<={{1'b0,sta{stage3_cout,stage3_sum}<={{stage2_a

我在做一个verilog编写的8位四级流水线加法器，这是我第一次做全流程的設计。从verilog设计编写、功能仿真、逻辑综合、时序分析然后做布局布线。现在卡在PT这了，不會做了，求助大神们帮帮忙！下面的程序：
moduleadder_pipeline(rst_n,clk,a,b,cin,sum);
parameter    DATA_SIZE = 8;
input rst_n;
input clk;
input [DATA_SIZE -1 : 0] a;
input [DATA_SIZE -1 : 0] b;
input cin;
output [DATA_SIZE: 0] sum;
reg [DATA_SIZE - 1: 0] a_r;
reg [DATA_SIZE - 1: 0] b_r;
reg cin_r;
reg [DATA_SIZE :0] sum;
reg [1:0]stage0_sum;
reg stage0_cout;
reg [DATA_SIZE - 1: 0] stage0_a_r;
reg [DATA_SIZE - 1: 0] stage0_b_r;
reg [3:0]stage1_sum;
reg stage1_cout;
reg [DATA_SIZE - 1: 0] stage1_a_r;
reg [DATA_SIZE - 1: 0] stage1_b_r;
reg [5:0]stage2_sum;
reg stage2_cout;
reg [DATA_SIZE - 1: 0] stage2_a_r;
reg [DATA_SIZE - 1: 0] stage2_b_r;
reg [7:0]stage3_sum;
reg stage3_cout;
always@(posedgeclk)
   if(!rst_n)
      begin
         a_r <= 8'd0;
         b_r <= 8'd0;
         cin_r <= 1'b0;
      end
   else
      begin
         a_r <= a;
         b_r <= b;
         cin_r <= cin;
      end
always@(posedgeclk)
   if(!rst_n)
      begin
         {stage0_cout,stage0_sum} <=3'd0;
         stage0_a_r <= 8'd0;
         stage0_b_r <= 8'd0;
      end
   else
      begin
            {stage0_cout,stage0_sum} <={1'b0,a_r[1:0]} + {1'b0,b_r[1:0]} + cin_r;
         stage0_a_r <= a_r;
         stage0_b_r <= b_r;
      end
always@(posedge clk)
   if(!rst_n)
      begin
         {stage1_cout,stage1_sum} <=5'd0;
         stage1_a_r <= 8'd0;
         stage1_b_r <= 8'd0;
      end
   else
      begin
         {stage1_cout,stage1_sum} <= {{1'b0,stage0_a_r[3:2]} + {1'b0,stage0_b_r[3:2]} + stage0_cout,stage0_sum };
         stage1_a_r <= stage0_a_r;
         stage1_b_r <= stage0_b_r;
      end
always@(posedge clk)
   if(!rst_n)
      begin
         {stage2_cout,stage2_sum} <=7'd0;
         stage2_a_r <= 8'd0;
         stage2_b_r <= 8'd0;
      end
   else
      begin
         {stage2_cout,stage2_sum} <= {{1'b0,stage1_a_r[5:4]} + {1'b0,stage1_b_r[5:4]} + stage1_cout,stage1_sum};
         stage2_a_r <= stage1_a_r;
         stage2_b_r <= stage1_b_r;
      end
always@(posedge clk)
   if(!rst_n)
      begin
         {stage3_cout,stage3_sum} <=9'd0;
      end
   else
      begin
         {stage3_cout,stage3_sum} <= {{stage2_a_r[7],stage2_a_r[7:6]} + {stage2_b_r[7],stage2_b_r[7:6]} +stage2_cout,stage2_sum };
      end
  always@(posedge clk)
   if(!rst_n)
      begin
         sum <= 9'd0;
      end
   else
      begin
         sum <={stage3_cout,stage3_sum};
      end

endmodule
接下来的时序分析，怎么用虚拟机做我就不会了

作者: another503 时间: 2020-3-2 09:19
太牛了，从前端到后端，

基本要靠flow支持的，要教会很累的，几句话说不清楚

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